1. Field of the Invention
The present invention relates to a method of forming a trench and to a method of forming a semiconductor device having a trench.
2. Description of the Related Art
For some time now, semiconductor devices have been employed in most electronic devices including information processing apparatuses and home appliances. Currents demands for information processing apparatus, such as computers, require that the apparatus posses a large processing capacity and a high processing speed. Thus, semiconductor devices of the information processing apparatus must also have a high response speed and a large storage capacity. This is achieved through the integration of the semiconductor device.
In general, the capacity of random access memory (RAM) chips has been improving according to Moores' law. Moores' law, postulated from empirical data, indicates that the storage capacity of memory chips has increased by a factor of four every three years. This increase has been accomplished through a combination of reducing the size of semiconductor devices installed on the chip, and increasing the length of the chip accordingly. The smaller the semiconductor device installed on the silicon chip becomes, the finer the interconnect lines of the semiconductor device must become. However, the signals running through the interconnect lines may interfere with each other when the interconnect lines are arranged close to one another. In fact, delays in the device will be caused by the interference when the spacing of the interconnect lines is below a predetermined value. The specific resistance of the metal used for forming the interconnect lines must be reduced in this situation if a high processing speed of the semiconductor devices is to be maintained.
Until recently, the interconnect lines of the semiconductor device were formed using aluminum (Al) or an aluminum alloy having a specific resistance of approximately 2.66 μΩ·cm. However, in 1998, International Business Machine Co. disclosed a method for forming an interconnect line with copper (Cu). Moreover, since then, various researchers have improved upon the method of forming interconnect lines or wiring using copper. In particular, a damascene process was developed in order to form copper interconnection lines or copper wiring. More specifically, a dual damascene process is often advantageously employed to form metal wiring and a contact all at once.
Recently, the damascene process for forming metal wiring of a semiconductor device or a bottom electrode of a capacitor has been preceded by etching an insulation layer to form a trench having a predetermined dimension in the insulation layer, wherein the damascene process entails forming a copper film in the trench using electroplating and chemical mechanical polishing (CMP) techniques. U.S. Pat. No. 6,259,128 (issued to Douglas R. Robert et. al.), Korean Patent Laid-Open Publication No. 2003-10507, and Korean Patent Laid-Open Publication No. 2003-2803 all disclose such methods of forming an insulation layer, a trench, a metal wiring and a capacitor.
FIGS. 1A and 1B illustrates a conventional method of forming a trench. Referring to FIG. 1A, an insulation layer 15 comprising an oxide or nitride is formed on a semiconductor substrate 10 such as a silicon wafer. A photoresist film (not shown) is then formed on the insulation layer 15. The photoresist film is exposed and developed to form a photoresist pattern 20 on the insulation layer 15. The photoresist pattern 20 is used as an etching mask during an etching process for forming the trench. Accordingly, the photoresist pattern 20 should have a height h and a width w sufficient for forming a trench having a desired width and depth. If the height of the photoresist pattern 20 is too small, the photoresist 20 may be completely consumed before the trench is not completely formed in the insulation film 15 during the etching process. In addition, the photoresist pattern 20 should have a relatively small width w because the trench becomes too narrow when the photoresist pattern 20 is too wide.
Generally, the photo resist pattern 20 on the insulation layer 15 should have an aspect ratio (a ratio of the height h relative to the width w) of more than about 3, as shown in FIG. 1A, for a satisfactory trench to be formed by etching the insulation layer 15 using the photoresist pattern 20 as an etching mask. However, as shown in FIG. 1B, the photoresist pattern 20 has an unstable structure when the photoresist pattern 20 has an aspect ratio of about 3− so much so that the photoresist pattern 20 may collapse on the insulation film 15. If an attempt to solve this problem is made by augmenting the width of the photoresist pattern 20, the width of the trench becomes too narrow (in an inversely proportional relation). Hence, copper (Cu) wiring may not be formed in the trench to a desired dimension by the damascene process because of limitations that the photoresist pattern 20 imposes on the dimensioning of the trench. Additionally, the trench may not be formed in the insulation layer 15 at all or the trench may not have accurate dimensions when the etching process for forming the trench is performed using a mask as a photoresist pattern 20 that has collapsed on the insulation layer 15. In this case, a defective semiconductor device may be produced, i.e., the yield of the semiconductor device manufacturing process is reduced. Furthermore, striations may be formed on the insulation layer 15 or on the metal wiring when a successive manufacturing process is performed while the photoresist pattern 20 is collapsed. In this case, a fatal manufacturing error may occur during the next manufacturing process.